library ieee;
use ieee.std_logic_1164.all;

entity sl2_tb is
end sl2_tb;

architecture behav of sl2_tb is
    component sl2
        port(
        a: in std_logic_vector(31 downto 0);
        y: out std_logic_vector(31 downto 0)
        );
    end component;
begin
    -- HACER!!!
end behav;
